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Evolutionary Optimisation of Neural Network Hardware Accelerators

Event details

Location: Online (Zoom)

Date: 3.11.2025

Time: 14:00-22:00 (CET)

Neural networks are not just the domain of large GPUs and supercomputers. Increasingly, they can also be found in simple embedded systems. However, these systems are limited in terms of computational and memory resources. This tutorial will show methods based on evolutionary algorithms for optimising both accelerators for specific networks and networks for specific accelerators.

It will also demonstrate how the targeted introduction of error into computation, improving the organisation of computational units and memory, can affect the overall efficiency of inference. Modifying the network architecture for better parameters in hardware will be demonstrated by using Capsule Networks as an example. Similarly, small Ternary Networks will be optimised for printed electronics.

Learning outcomes

Participants will gain an overview of the category of smaller networks used in embedded systems and advanced optimisation techniques. They will also learn about power estimation techniques, mapping issues to compute units and the concept of approximate computing.

Prerequisites

The course is suitable for beginners and has no technical requirements.

Registration for the event

Registration is obligatory, and the capacity is limited to 60 participants.

The course is free of charge for all participants.